Invention Grant
- Patent Title: Method for integrated circuit patterning
- Patent Title (中): 集成电路图案化方法
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Application No.: US14088569Application Date: 2013-11-25
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Publication No.: US09129814B2Publication Date: 2015-09-08
- Inventor: Szu-Ping Tung , Huang-Yi Huang , Neng-Jye Yang , Ching-Hua Hsieh
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/311
- IPC: H01L21/311 ; H01L21/302 ; H01L21/033

Abstract:
A method of forming a target pattern includes forming a plurality of lines over a substrate with a first mask and forming a spacer layer over the substrate, over the plurality of lines, and onto sidewalls of the plurality of lines. The method further includes removing at least a portion of the spacer layer to expose the plurality of lines and the substrate. The method further includes shrinking the spacer layer disposed onto the sidewalls of the plurality of lines and removing the plurality of lines thereby resulting in a patterned spacer layer over the substrate.
Public/Granted literature
- US20150147886A1 Method For Integrated Circuit Patterning Public/Granted day:2015-05-28
Information query
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