Invention Grant
- Patent Title: Formation of silicide contacts in semiconductor devices
- Patent Title (中): 在半导体器件中形成硅化物触点
-
Application No.: US14157927Application Date: 2014-01-17
-
Publication No.: US09129842B2Publication Date: 2015-09-08
- Inventor: Yan-Ming Tsai , Wei-Jung Lin , Fang-Cheng Chen , Chii-Ming Wu
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L27/092 ; H01L21/324 ; H01L29/45 ; H01L29/16 ; H01L29/161 ; H01L21/285 ; H01L21/265
Abstract:
Methods of forming silicide contacts in semiconductor devices are presented. An exemplary method comprises providing a semiconductor substrate having an n-type field effect transistor (nFET) region and a p-type field effect transistor (pFET) region; performing a pre-amorphized implantation (PAI) process to an n-type doped silicon (Si) feature in on the nFET region and a p-type doped silicon germanium (SiGe) feature in the pFET region, thereby forming an n-type amorphous silicon (a-Si) feature and a p-type amorphous silicon germanium (a-SiGe) feature; depositing a metal layer over each of the a-Si and a-SiGe features; performing an annealing process on the semiconductor device with a temperature ramp-up rate tuned according to a silicide growth rate difference between the n-type a-Si and the p-type a-SiGe features. During the annealing process the n-type a-Si and the p-type a-SiGe features are completely consumed, and amorphous silicide features are formed in the nFET and pFET regions.
Public/Granted literature
- US20150206881A1 Formation Of Silicide Contacts In Semiconductor Devices Public/Granted day:2015-07-23
Information query
IPC分类:
