Invention Grant
- Patent Title: Solder bump joining structure with low resistance joining member
- Patent Title (中): 具有低电阻接合部件的焊点接合结构
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Application No.: US14489932Application Date: 2014-09-18
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Publication No.: US09129884B2Publication Date: 2015-09-08
- Inventor: Kei Murayama
- Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
- Applicant Address: JP Nagano-ken
- Assignee: Shinko Electric Industries Co., Ltd.
- Current Assignee: Shinko Electric Industries Co., Ltd.
- Current Assignee Address: JP Nagano-ken
- Agency: Fish & Richardson P.C.
- Priority: JP2013-207498 20131002
- Main IPC: H01L23/498
- IPC: H01L23/498 ; H01L23/00 ; H01L23/538

Abstract:
A semiconductor device is provided with a wiring substrate including a connection pad, a joining member joined with the connection pad, and a semiconductor chip including a connection terminal electrically connected to the connection pad via the joining member. The joining member consists of a first intermetallic compound layer formed at a boundary between the connection pad and the joining member, a second intermetallic compound layer formed at a boundary between the connection terminal and the joining member, a third intermetallic compound layer composed of an intermetallic compound of Cu6Sn5 or (Cu,Ni)6Sn5 and formed between the first intermetallic compound layer and the second intermetallic compound layer, and discrete metal grains, each being composed of a simple substance of Bi, in the third intermetallic compound layer. Surfaces of each of the metal grains are completely covered by the third intermetallic compound layer so that the metal grains do not form a layer.
Public/Granted literature
- US20150091162A1 SEMICONDUCTOR DEVICE Public/Granted day:2015-04-02
Information query
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