Invention Grant
- Patent Title: Self-aligned double spacer patterning process
- Patent Title (中): 自对准双间隔图案化工艺
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Application No.: US14098315Application Date: 2013-12-05
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Publication No.: US09129906B2Publication Date: 2015-09-08
- Inventor: Yung-Hsu Wu , Tsung-Min Huang , Cheng-Hsiung Tsai , Chung-Ju Lee , Tien-I Bao , Shau-Lin Shue
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L21/4763
- IPC: H01L21/4763 ; H01L21/308 ; H01L21/768

Abstract:
Embodiments of the present disclosure are a method of forming a semiconductor device and methods of patterning a semiconductor device. An embodiment is a method of forming a semiconductor device, the method including forming a first hard mask layer over a semiconductor device layer, the first hard mask layer comprising a metal-containing material, forming a second hard mask layer over the first hard mask layer, and forming a first set of metal-containing spacers over the second hard mask layer. The method further includes patterning the second hard mask layer using the first set of metal-containing spacers as a mask, forming a second set of metal-containing spacers on sidewalls of the patterned second hard mask layer, and patterning the first hard mask layer using the second set of metal-containing spacers as a mask.
Public/Granted literature
- US20150162205A1 Self-Aligned Double Spacer Patterning Process Public/Granted day:2015-06-11
Information query
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