Invention Grant
- Patent Title: Multi-chip packages with reduced power distribution network noise
- Patent Title (中): 具有降低配电网络噪声的多芯片封装
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Application No.: US13646477Application Date: 2012-10-05
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Publication No.: US09129935B1Publication Date: 2015-09-08
- Inventor: Karthik Chandrasekar , Arifur Rahman , Jeffrey Tyhach
- Applicant: Karthik Chandrasekar , Arifur Rahman , Jeffrey Tyhach
- Applicant Address: US CA San Jose
- Assignee: Altera Corporation
- Current Assignee: Altera Corporation
- Current Assignee Address: US CA San Jose
- Agency: Treyz Law Group
- Agent Jason Tsai
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L49/02 ; H01L21/50 ; H01L21/48 ; H01L23/498 ; H01L25/065

Abstract:
A multi-chip package that includes multiple integrated circuits is provided. An integrated circuit in the multi-chip package may be mounted on an interposer. The interposer may be mounted on a package substrate. The integrated circuit may have internal power supply terminals coupled to on-package decoupling (OPD) capacitor circuitry that are formed as part of the package substrate. The power supply terminals on the integrated circuit may be coupled to conductive routing paths and through-silicon vias (TSVs) in the interposer via microbumps. The through-silicon vias in the interposer may be coupled to the OPD capacitor circuitry via flip-chip bumps. The conductive routing paths and the TSVs in the interposer may be coupled to the internal integrated circuit power supply terminals in a way that minimizes power supply resonance noise.
Information query
IPC分类: