Invention Grant
US09129938B1 Methods of forming germanium-containing and/or III-V nanowire gate-all-around transistors
有权
形成含锗和/或III-V纳米线栅极全环晶体管的方法
- Patent Title: Methods of forming germanium-containing and/or III-V nanowire gate-all-around transistors
- Patent Title (中): 形成含锗和/或III-V纳米线栅极全环晶体管的方法
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Application No.: US14195359Application Date: 2014-03-03
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Publication No.: US09129938B1Publication Date: 2015-09-08
- Inventor: Kangguo Cheng , Bruce B. Doris , Pouya Hashemi , Ali Khakifirooz , Alexander Reznicek
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Agent Louis J. Percello, Esq.
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L29/423 ; H01L21/02 ; H01L21/306 ; H01L21/308 ; H01L29/26 ; H01L29/06

Abstract:
Methods of forming gate-all-around transistors which include a germanium-containing nanowire and/or an III-V compound semiconductor nanowire. Each method includes the growth of a germanium-containing material or an III-V compound semiconductor material that includes an upper portion and a lower portion within a nano-trench and on an exposed surface of a semiconductor layer. In some instances, the upper portion of the grown semiconductor material is used as the semiconductor nanowire. In other instances, the upper portion is removed and then a semiconductor etch stop layer and a nanowire template semiconductor material of a Ge-containing material or an III-V compound semiconductor material can be formed atop the lower portion. Upon subsequent processing, each nanowire template semiconductor material provides a semiconductor nanowire.
Public/Granted literature
- US20150249139A1 METHODS OF FORMING GERMANIUM-CONTAINING AND/OR III-V NANOWIRE GATE-ALL-AROUND TRANSISTORS Public/Granted day:2015-09-03
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