Invention Grant
US09129968B2 Schemes for forming barrier layers for copper in interconnect structures
有权
用于在互连结构中形成铜的阻挡层的方案
- Patent Title: Schemes for forming barrier layers for copper in interconnect structures
- Patent Title (中): 用于在互连结构中形成铜的阻挡层的方案
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Application No.: US14263842Application Date: 2014-04-28
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Publication No.: US09129968B2Publication Date: 2015-09-08
- Inventor: Chen-Hua Yu , Hai-Ching Chen , Tien-I Bao
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L21/40
- IPC: H01L21/40 ; H01L21/48 ; H01L21/52 ; H01L23/532 ; H01L21/768

Abstract:
A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided.
Public/Granted literature
- US20140231999A1 Schemes for Forming Barrier Layers for Copper in Interconnect Structures Public/Granted day:2014-08-21
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