Fabricating a vertical thin film transistor includes printing a polymeric inhibitor in a cap pattern on a structural polymer layer on a substrate. A polymeric inhibitor is printed in a gate pattern on the substrate, in a dielectric pattern on the substrate, in a semiconductor pattern on a patterned conformal dielectric layer, and in an electrode pattern. The electrode pattern includes an open area over a portion of a reentrant profile that allows the polymeric inhibitor to wick along the reentrant profile in the open area. Fabrication of the vertical transistor also includes depositing an inorganic thin film, a first conductive thin film, a dielectric thin film, a semiconductor thin film, and a second conductive thin film using an atomic layer deposition (ALD) process.