An integrated circuit comprises a plurality of lateral devices and quasi vertical devices formed in a same semiconductor die. The quasi vertical devices include two trenches. A first trench is formed between a first drain/source region and a second drain/source region. The first trench comprises a dielectric layer formed in a bottom portion of the first trench and a gate region formed in an upper portion of the first trench. A second trench is formed on an opposite side of the second drain/source region from the first trench. The second trench is coupled between the second drain/source region and a buried layer, wherein the second trench is of a same depth as the first trench.