Synthesized signal generation circuits are provided to correspond to a U-coil, a V-coil, a W-coil, respectively, and generate synthesized signals by synthesizing a first command signal and a second command signal generated by a command signal generation circuit. CPU output terminals output the synthesized signals. Signal wires are provided with one ends being connected electrically to the CPU output terminals, respectively, and other ends being connected electrically to IC input terminals of a driver IC, respectively. Gate signal generation circuits separate the synthesized signals applied to the IC input terminals to generate first gate signals as gate signals for high-side FETs and second gate signals as gate signals for low-side FETs.