Invention Grant
- Patent Title: Controllable polarity FET based arithmetic and differential logic
- Patent Title (中): 基于可控极性FET的算术和差分逻辑
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Application No.: US13960964Application Date: 2013-08-07
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Publication No.: US09130568B2Publication Date: 2015-09-08
- Inventor: Luca Gaetano Amaru , Pierre-Emmanuel Julien Marc Gaillardon , Giovanni De Micheli
- Applicant: ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)
- Applicant Address: CH
- Assignee: ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)
- Current Assignee: ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)
- Current Assignee Address: CH
- Agency: Sheridan Ross P.C.
- Priority: EP12179928 20120809
- Main IPC: H03K19/21
- IPC: H03K19/21 ; H03K19/23 ; H03K17/687 ; H03K19/20
Abstract:
A logic gate with three inputs A, B, and C, and one output implementing a function MAJ(A,B,C)=A*B+B*C+A*C comprising two mutually exclusive transmission gates (TGs) connected in series, based on two parallel double-gate controllable polarity devices, a polarity of each being controlled by input A and a conduction being controlled by input B, or vice-versa, in opposite polarities, and that route either an input A or C from one side of the transmission gates to the output.
Public/Granted literature
- US20140043060A1 CONTROLLABLE POLARITY FET BASED ARITHMETIC AND DIFFERENTIAL LOGIC Public/Granted day:2014-02-13
Information query
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