Invention Grant
- Patent Title: PLL circuit
- Patent Title (中): PLL电路
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Application No.: US14222495Application Date: 2014-03-21
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Publication No.: US09130577B2Publication Date: 2015-09-08
- Inventor: Takuya Sahara
- Applicant: Yamaha Corporation
- Applicant Address: JP Hamamatsu-shi
- Assignee: Yamaha Corporation
- Current Assignee: Yamaha Corporation
- Current Assignee Address: JP Hamamatsu-shi
- Agency: Morrison & Foerster LLP
- Priority: JP2013-061190 20130323
- Main IPC: H03L7/08
- IPC: H03L7/08 ; H03L7/14

Abstract:
A PLL circuit generating a generated clock in synchronization with an external clock by a phase locked loop includes a first detector for detecting whether or not the generated clock is in synchronization with the external clock, and a measuring device for measuring at least one of a high time from a rise to a fall of the external clock and a low time from a fall to a rise thereof. In a state that the generated clock and the external clock are in synchronization, when it is detected that a fluctuation of the high time or the low time becomes equal to or more than a predetermined value, the PLL circuit fixes a frequency of the generated clock to a frequency outputted at this time point, and continues output of the generated clock having the fixed frequency.
Public/Granted literature
- US20140285245A1 PLL CIRCUIT Public/Granted day:2014-09-25
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