Invention Grant
US09135965B2 Memory controller and method for interleaving DRAM and MRAM accesses
有权
用于交错DRAM和MRAM访问的存储器控制器和方法
- Patent Title: Memory controller and method for interleaving DRAM and MRAM accesses
- Patent Title (中): 用于交错DRAM和MRAM访问的存储器控制器和方法
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Application No.: US13328867Application Date: 2011-12-16
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Publication No.: US09135965B2Publication Date: 2015-09-15
- Inventor: Syed M. Alam , Thomas Andre , Dietmar Gogl
- Applicant: Syed M. Alam , Thomas Andre , Dietmar Gogl
- Applicant Address: US AZ Chandler
- Assignee: Everspin Technologies, Inc.
- Current Assignee: Everspin Technologies, Inc.
- Current Assignee Address: US AZ Chandler
- Main IPC: G11C11/00
- IPC: G11C11/00 ; G11C7/10 ; G11C11/4076 ; G11C8/04
Abstract:
A memory controller and method for interleaving volatile and non-volatile memory different latencies and page sizes are described wherein a single DDR3 memory controller communicates with a number of memory modules comprising of at least non-volatile memory, e.g., spin torque magnetic random access memory, integrated in a different Rank or Channel with a volatile memory, e.g., dynamic random access memory (DRAM).
Public/Granted literature
- US20120155160A1 MEMORY CONTROLLER AND METHOD FOR INTERLEAVING DRAM AND MRAM ACCESSES Public/Granted day:2012-06-21
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