Invention Grant
- Patent Title: Method for integrated circuit patterning
- Patent Title (中): 集成电路图案化方法
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Application No.: US14134027Application Date: 2013-12-19
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Publication No.: US09136106B2Publication Date: 2015-09-15
- Inventor: Chieh-Han Wu , Chung-Ju Lee , Cheng-Hsiung Tsai , Ming-Feng Shieh , Ru-Gun Liu , Tien-I Bao , Shau-Lin Shue
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L21/46 ; H01L21/02 ; H01L21/027 ; H01L21/308

Abstract:
A method of forming a target pattern includes forming a plurality of lines over a substrate with a first mask and forming a first spacer layer over the substrate, over the plurality of lines, and onto sidewalls of the plurality of lines. The plurality of lines is removed, thereby providing a patterned first spacer layer over the substrate. The method further includes forming a second spacer layer over the substrate, over the patterned first spacer layer, and onto sidewalls of the patterned first spacer layer, and forming a patterned material layer over the second spacer layer with a second mask. Whereby, the patterned material layer and the second spacer layer collectively define a plurality of trenches.
Public/Granted literature
- US20150179435A1 Method For Integrated Circuit Patterning Public/Granted day:2015-06-25
Information query
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