An ESD protection device includes a semiconductor substrate including input/output electrodes and a rewiring layer provided on a surface of the semiconductor substrate. An ESD protection circuit is provided on or in an outer layer of the semiconductor substrate, and the input/output electrodes are connected to the ESD protection circuit. The rewiring layer includes interlayer wiring lines, in-plane wiring lines, and post electrodes. First ends of the interlayer wiring lines disposed in the thickness direction are connected to the input/output electrodes disposed on the surface of the semiconductor substrate, and second ends of the interlayer wiring lines are connected to first ends of the in-plane wiring lines routed in plan view. Prismatic post electrodes are provided between second ends of the in-plane wiring lines and terminal electrodes.