Invention Grant
US09141561B2 Master circuits having dynamic priority leads coupled with memory controller
有权
具有动态优先级的主电路与存储器控制器耦合
- Patent Title: Master circuits having dynamic priority leads coupled with memory controller
- Patent Title (中): 具有动态优先级的主电路与存储器控制器耦合
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Application No.: US13672082Application Date: 2012-11-08
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Publication No.: US09141561B2Publication Date: 2015-09-22
- Inventor: Serge Bernard Lasserre , Marouane Berrada , Stephen Busch , Denis Beaudoin
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Lawrence J. Bassuk; Charles A. Brill; Frank D. Cimino
- Priority: EP12290371 20121025
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F13/00 ; G11C11/406
Abstract:
A system includes multiple master devices and at least one memory refresh scheduler. When a master device needs higher priority for memory access, the master device sends a dynamic priority signal to the memory refresh scheduler and in response, the memory refresh scheduler changes its policy for issuing refresh commands.
Public/Granted literature
- US20140122790A1 DYNAMIC PRIORITY MANAGEMENT OF MEMORY ACCESS Public/Granted day:2014-05-01
Information query
