Invention Grant
US09141831B2 Scheduler, security context cache, packet processor, and authentication, encryption modules
有权
调度器，安全上下文缓存，数据包处理器和认证，加密模块
- Patent Title: Scheduler, security context cache, packet processor, and authentication, encryption modules
- Patent Title (中): 调度器，安全上下文缓存，数据包处理器和认证，加密模块
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Application No.: US13165190Application Date: 2011-06-21
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Publication No.: US09141831B2Publication Date: 2015-09-22
- Inventor: Amritpal Singh Mundra , Denis Roland Beaudoin
- Applicant: Amritpal Singh Mundra , Denis Roland Beaudoin
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Lawrence J. Bassuk; Frank D. Cimino
- Main IPC: G06F21/72
- IPC: G06F21/72 ; H04L9/06 ; H04L29/06
Abstract:
An electronic circuit (200) includes one or more programmable control-plane engines (410, 460) operable to process packet header information and form at least one command, one or more programmable data-plane engines (310, 320, 370) selectively operable for at least one of a plurality of cryptographic processes selectable in response to the at least one command, and a programmable host processor (100) coupled to such a data-plane engine (310) and such a control-plane engine (410). Other processors, circuits, devices and systems and processes for their operation and manufacture are disclosed.
Public/Granted literature
- US20120011351A1 Security Processing Engines, Circuits and Systems and Adaptive Processes and Other Processes Public/Granted day:2012-01-12
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