Invention Grant
US09142315B2 Methods and systems for adjusting NVM cell bias conditions for read/verify operations to compensate for performance degradation
有权
用于调整NVM单元偏置条件以进行读取/验证操作以补偿性能下降的方法和系统
- Patent Title: Methods and systems for adjusting NVM cell bias conditions for read/verify operations to compensate for performance degradation
- Patent Title (中): 用于调整NVM单元偏置条件以进行读取/验证操作以补偿性能下降的方法和系统
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Application No.: US13557449Application Date: 2012-07-25
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Publication No.: US09142315B2Publication Date: 2015-09-22
- Inventor: Fuchen Mu , Benjamin A. Schmid , Yanzhuo Wang
- Applicant: Fuchen Mu , Benjamin A. Schmid , Yanzhuo Wang
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agency: Egan, Peterman & Enders LLP.
- Main IPC: G11C11/34
- IPC: G11C11/34 ; G11C16/34 ; G11C11/56 ; G11C16/04

Abstract:
Methods and systems are disclosed for adjusting read/verify bias conditions for non-volatile memory (NVM) cells to improve performance and product lifetime of NVM systems. System embodiments include integrated NVM systems having a NVM controller, a bias voltage generator, and an NVM cell array. Further, the NVM systems can store performance degradation information and read/verify bias condition information within storage circuitry. The disclosed embodiments adjust read/verify bias conditions for the NVM cells based upon performance degradation determinations, for example, temperature-based performance degradation determinations.
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