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US09142557B2 Cost effective method of forming embedded DRAM capacitor 有权
形成嵌入式DRAM电容器的成本有效的方法

Cost effective method of forming embedded DRAM capacitor
Abstract:
A high capacitance embedded metal interconnect capacitor and associated fabrication processes are disclosed for using a directional barrier metal formation sequence in a dual damascene copper process to form multi-layer stacked copper interconnect structure having reduced barrier metal layer formation at the bottom of each via hole so that the multi-layer stacked copper interconnect structure may be readily removed and replaced with high capacitance MIM capacitor layers.
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