Invention Grant
- Patent Title: SOI substrate with acceptor-doped layer
- Patent Title (中): 具有受主掺杂层的SOI衬底
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Application No.: US13915307Application Date: 2013-06-11
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Publication No.: US09142565B2Publication Date: 2015-09-22
- Inventor: Yoshitomo Sagae , Fumio Sasaki , Ryoichi Ohara
- Applicant: Kabushiki Kaisha Toshiba
- Applicant Address: JP Minato-ku
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Minato-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2007-062137 20070312
- Main IPC: H01L27/12
- IPC: H01L27/12 ; H01L21/762 ; H01L23/552 ; H01L23/66 ; H01L29/786 ; H01L29/16 ; H01L21/8238
Abstract:
A semiconductor device includes a SOI substrate including a silicon substrate, an oxide layer on the silicon substrate, and a silicon layer on the oxide layer; a source region and a drain region formed in the silicon layer; and an acceptor-doped layer formed between the oxide layer and the silicon substrate, the acceptor-doped layer being doped with acceptors.
Public/Granted literature
- US20130270640A1 SEMICONDUCTOR DEVICE Public/Granted day:2013-10-17
Information query
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