Invention Grant
US09147498B2 Circuit arrangement, a method for testing a supply voltage provided to a test circuit, and a method for repairing a voltage source
有权
电路布置，用于测试提供给测试电路的电源电压的方法以及修复电压源的方法
- Patent Title: Circuit arrangement, a method for testing a supply voltage provided to a test circuit, and a method for repairing a voltage source
- Patent Title (中): 电路布置，用于测试提供给测试电路的电源电压的方法以及修复电压源的方法
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Application No.: US13862513Application Date: 2013-04-15
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Publication No.: US09147498B2Publication Date: 2015-09-29
- Inventor: Leonardo Henrique Bonet Zordan , Alberto Bosio , Patrick Girard , Nabil Badereddine
- Applicant: Leonardo Henrique Bonet Zordan , Alberto Bosio , Patrick Girard , Nabil Badereddine
- Applicant Address: DE Neubiberg FR Paris FR Montpellier
- Assignee: INTEL DEUTSCHLAND GMBH,CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE (CNRS),UNIVERSITE DE MONTPELLIER 2
- Current Assignee: INTEL DEUTSCHLAND GMBH,CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE (CNRS),UNIVERSITE DE MONTPELLIER 2
- Current Assignee Address: DE Neubiberg FR Paris FR Montpellier
- Main IPC: G11C11/00
- IPC: G11C11/00 ; G11C29/02 ; G11C29/44 ; G11C11/41
Abstract:
A circuit arrangement may include: a memory, composed of a memory cell array, including a plurality of memory cells, and a peripheral circuitry; a voltage source configured to provide at least one supply voltage; a test circuit integrated with the memory cell array and the voltage source, wherein the test circuit receives the supply voltage; the test circuit including: at least one test memory cell; at least one failure detection circuit configured to detect a data retention failure in the at least one test memory cell.
Public/Granted literature
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