A power management circuit for a liquid crystal display device is disclosed. The power management circuit includes one or more power generating circuits, for receiving one or more input voltages and generating one or more output voltages, respectively; a gate pulse modulation circuit, coupled between a gate high-level voltage source and a discharging control terminal, for generating a gate control signal; and a discharging controller, coupled to the discharging control terminal, for providing a discharging path for the gate pulse modulation circuit, wherein one of the gate pulse modulation circuit and the discharging controller is further coupled to a power supply such that the gate pulse modulation circuit discharges to the power supply during a gate discharging period, and the power supply is one of the one or more input voltages and the one or more output voltages.