A memory device includes a plurality of resistive memory units configured to receive a voltage of a corresponding line of a plurality of program/read lines, a plurality of switch units configured to each electrically connect a corresponding one of the resistive memory units with a corresponding line of a plurality of column lines in response to a voltage of a corresponding line of a plurality of row lines, where the program/read lines correspond to the row lines, respectively, a row control circuit configured to turn on the switch units by selecting at least one of the row lines and apply an external voltage to a program/read line corresponding to the selected row line in a first test mode, and a column control circuit configured to select at least one of the column lines and couple the selected column line with a ground voltage terminal in the first test mode.