Invention Grant
- Patent Title: Microelectronic package and stacked microelectronic assembly and computing system containing same
- Patent Title (中): 微电子封装和堆叠微电子组装和计算系统包含相同
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Application No.: US13976102Application Date: 2011-12-20
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Publication No.: US09159649B2Publication Date: 2015-10-13
- Inventor: Pramod Malatkar , Drew W. Delaney , Rahul N. Manepalli , Dilan Seneviratne
- Applicant: Pramod Malatkar , Drew W. Delaney , Rahul N. Manepalli , Dilan Seneviratne
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agent Kenneth A. Nelson
- International Application: PCT/US2011/066049 WO 20111220
- International Announcement: WO2013/095363 WO 20130627
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/498 ; H01L25/10

Abstract:
A microelectronic package comprises a die (110, 210) and a plurality of electrically conductive layers (120, 220) and electrically insulating layers (130, 230), including a first electrically insulating layer (131, 231) closer to the die than any other electrically insulating layer) and second (132, 232) and third electrically insulating layers (233). Each electrically insulating layer has a corresponding glass transition temperature, coefficient of thermal expansion, and modulus of elasticity. The modulus of elasticity of the second electrically insulating layer is greater than that for the first electrically insulating layer, while CTE1 for the second electrically insulating layer is greater than CTE1 for the first. CTE2 for the third electrically insulating layer is less than CTE2 for the first electrically insulating layer. In an embodiment an electrically insulating layer is a glass cloth layer (140) that is an outermost layer of the microelectronic package.
Public/Granted literature
- US20130270719A1 MICROELECTRONIC PACKAGE AND STACKED MICROELECTRONIC ASSEMBLY AND COMPUTING SYSTEM CONTAINING SAME Public/Granted day:2013-10-17
Information query
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