Invention Grant
US09165652B2 Split-gate memory cells having select-gate sidewall metal silicide regions and related manufacturing methods
有权
具有选择侧壁金属硅化物区域的分离栅极存储单元和相关的制造方法
- Patent Title: Split-gate memory cells having select-gate sidewall metal silicide regions and related manufacturing methods
- Patent Title (中): 具有选择侧壁金属硅化物区域的分离栅极存储单元和相关的制造方法
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Application No.: US13589249Application Date: 2012-08-20
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Publication No.: US09165652B2Publication Date: 2015-10-20
- Inventor: Sung-Taeg Kang , Cheong M. Hong
- Applicant: Sung-Taeg Kang , Cheong M. Hong
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agency: Egan, Peterman & Enders LLP.
- Main IPC: H01L29/792
- IPC: H01L29/792 ; H01L29/423 ; G11C16/04 ; H01L21/28 ; H01L29/788
Abstract:
Split-gate non-volatile memory (NVM) cells having select-gate sidewall metal silicide regions are disclosed along with related manufacturing methods. Spacer etch processing steps are used to expose sidewall portions of select gates. Metal silicide regions are then formed within these sidewall portions of the select gates. Further, metal silicide regions can also be formed in top portions of the select gates. Further, the select gates can also be formed with one or more notches. By expanding the size of the metal silicide region to include the sidewall portion of the select gate, the select gate wordline (e.g., polysilicon) resistance is reduced for split-gate NVM arrays, the electrical contact to the select gate is improved, and performance of the select-gate NVN cell is improved.
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