Invention Grant
- Patent Title: Methods of forming low resistance contacts
- Patent Title (中): 形成低电阻触点的方法
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Application No.: US14190226Application Date: 2014-02-26
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Publication No.: US09165838B2Publication Date: 2015-10-20
- Inventor: Chun-Wen Nieh , Hung-Chang Hsu , Wei-Jung Lin , Yan-Ming Tsai , Chen-Ming Lee , Mei-Yun Wang
- Applicant: Taiwan Semiconductor Manufacturing Company Limited
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company Limited
- Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
- Current Assignee Address: TW Hsinchu
- Agency: Jones Day
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L21/8238 ; H01L21/283 ; H01L27/092 ; H01L29/45

Abstract:
Methods for forming electrical contacts are provided. First and second FETs are formed over a semiconductor substrate. Openings are etched in a dielectric layer formed over the substrate, where the openings extend to source and drain regions of the FETs. A hard mask is formed over the source and drain regions of FETs. A first portion of the hard mask is removed, where the first portion is formed over the source and drain regions of the first FET. First silicide layers are formed over the source and drain regions of the first FET. A second portion of the hard mask is removed, where the second portion is formed over the source and drain regions of the second FET. Second silicide layers are formed over the source and drain regions of the second FET. A metal layer is deposited within the openings to fill the openings.
Public/Granted literature
- US20150243565A1 METHODS OF FORMING LOW RESISTANCE CONTACTS Public/Granted day:2015-08-27
Information query
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