Invention Grant
US09165944B2 Semiconductor device including SOI butted junction to reduce short-channel penalty
有权
半导体器件包括SOI对接结,以减少短沟道损耗
- Patent Title: Semiconductor device including SOI butted junction to reduce short-channel penalty
- Patent Title (中): 半导体器件包括SOI对接结,以减少短沟道损耗
-
Application No.: US14047189Application Date: 2013-10-07
-
Publication No.: US09165944B2Publication Date: 2015-10-20
- Inventor: Viorel Ontalus , Robert R. Robison , Xin Wang
- Applicant: International Business Machines Corporation
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Cantor Colburn LLP
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L27/12 ; H01L21/84 ; H01L21/8234 ; H01L21/8238

Abstract:
A semiconductor device comprises first and second gate stacks formed on a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes a dielectric layer interposed between a bulk substrate layer and an active semiconductor layer. A first extension implant portion is disposed adjacent to the first gate stack and a second extension implant portion is disposed adjacent to the second gate stack. A halo implant extends continuously about the trench. A butting implant extends between the trench and the dielectric layer. An epitaxial layer is formed at the exposed region such that the butting implant is interposed between the epitaxial layer and the dielectric layer.
Public/Granted literature
- US20150097243A1 SEMICONDUCTOR DEVICE INCLUDING SOI BUTTED JUNCTION TO REDUCE SHORT-CHANNEL PENALTY Public/Granted day:2015-04-09
Information query
IPC分类: