Invention Grant
US09166057B2 Semiconductor device having the bottom gate type transistor formed in a wiring layer
有权
具有底栅型晶体管的半导体器件形成在布线层中
- Patent Title: Semiconductor device having the bottom gate type transistor formed in a wiring layer
- Patent Title (中): 具有底栅型晶体管的半导体器件形成在布线层中
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Application No.: US14138162Application Date: 2013-12-23
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Publication No.: US09166057B2Publication Date: 2015-10-20
- Inventor: Kishou Kaneko , Hiroshi Sunamura , Yoshihiro Hayashi
- Applicant: RENESAS ELECTRONICS CORPORATION
- Applicant Address: JP Kanagawa
- Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee Address: JP Kanagawa
- Agency: Young & Thompson
- Priority: JP2012-286074 20121227
- Main IPC: H01L29/10
- IPC: H01L29/10 ; H01L21/70 ; H01L23/48 ; H01L21/00 ; H01L29/786 ; H01L27/12
Abstract:
The present invention makes it possible to increase the selectivity of a gate insulation film in an active element formed in a wiring layer.A semiconductor device according to the present invention has a bottom gate type transistor using an antireflection film formed over an Al wire in a wiring layer as a gate wire.
Public/Granted literature
- US20140183525A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE Public/Granted day:2014-07-03
Information query
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