Nonvolatile memory devices and methods of operating the same
Abstract:
Nonvolatile memory devices including three transistor unit cells are provided. The nonvolatile memory device includes a selection transistor having a first terminal and a second terminal, a first charge trap transistor electrically connected in series to the first terminal of the selection transistor, a second charge trap transistor electrically connected in series to the second terminal of the selection transistor, and a word line electrically connected to gate electrodes of the selection transistor, the first charge trap transistor and the second charge trap transistor. Related methods are also provided.
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