Invention Grant
- Patent Title: Method for assembling a chip on a substrate
- Patent Title (中): 在芯片上组装芯片的方法
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Application No.: US12576542Application Date: 2009-10-09
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Publication No.: US09167703B2Publication Date: 2015-10-20
- Inventor: Laurent Vivet , Jean-Michel Morelle , Sandra Dimelli , Laurent Deneu-Fontaine , Romaric Lenoir
- Applicant: Laurent Vivet , Jean-Michel Morelle , Sandra Dimelli , Laurent Deneu-Fontaine , Romaric Lenoir
- Applicant Address: FR Creteil
- Assignee: VALEO ETUDES ELECTRONIQUES
- Current Assignee: VALEO ETUDES ELECTRONIQUES
- Current Assignee Address: FR Creteil
- Agency: Oliff PLC
- Priority: FR0856876 20081010
- Main IPC: H05K3/34
- IPC: H05K3/34 ; B23K1/005 ; H01L23/00 ; B23K3/06

Abstract:
In this method, a vertical stack is formed on an axis coinciding substantially with the gravity direction and comprising, from top to bottom: the element; the mass in a solid state; and the substrate. The mass is then heated so as to cause it to pass into a liquid state enabling it to spread on the substrate. More particularly, after the stack has been formed, the element is left free to move vertically, and during heating, variation in the vertical position of the element is measured.
Public/Granted literature
- US20100139089A1 METHOD AND A DEVICE FOR ASSEMBLING A CHIP ON A SUBSTRATE BY PROVIDING A SOLDER-FORMING MASS Public/Granted day:2010-06-10
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