Invention Grant
- Patent Title: Unit fill for integrated circuit design for manufacturing
- Patent Title (中): 单元填充集成电路设计制造
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Application No.: US14156877Application Date: 2014-01-16
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Publication No.: US09171119B2Publication Date: 2015-10-27
- Inventor: Nandagoutami Aenuganti , Kuldeep Singh
- Applicant: Oracle International Corporation
- Applicant Address: US CA Redwood City
- Assignee: ORACLE INTERNATIONAL CORPORATION
- Current Assignee: ORACLE INTERNATIONAL CORPORATION
- Current Assignee Address: US CA Redwood City
- Agency: Marsh Fischmann & Breyfogle LLP
- Agent Daniel J. Sherwinter
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
Embodiments include systems and methods for implementing a dummy fill flow in a processor design that points to a library of fill shapes that are associated with (e.g., defined and supported according to) a particular foundry process. For example, a set of cell types is generated in accordance with a foundry process definition, so that each unit cell type has a unique type identifier and an associated polygon definition. These cell types can be stored as a cell library. An automated fill flow can generate a dummy fill of an integrated circuit geometry with respective shape fills having shape cells that each point to one of the cell types in the cell library. Some implementations can use the cell library to stream in and instantiate the fill in the geometric design of the integrated circuit.
Public/Granted literature
- US20150186584A1 UNIT FILL FOR INTEGRATED CIRCUIT DESIGN FOR MANUFACTURING Public/Granted day:2015-07-02
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