Embodiments include systems and methods for using a shared virtual ground to implement a dual memory bitcell. Some embodiments of the dual memory bitcell described herein operate substantially as would two adjacent conventional bitcells, but with reduced power, reduced area, and other features. For example, each of two memory bitcells can be coupled with a write bitline, a virtual ground line, and a respective write wordline. The virtual ground is configured to be switched according to the write bitline. In such a configuration, the value stored by the memory bitcells can be a function of the write bitline and the virtual ground line (e.g., when the respective write word line of the memory bitcell is asserted). Certain embodiments can include a novel physical layout of the dual memory bitcell. Some implementations of the novel physical layout can include changes to the physical memory bitcell components and to one or more metal layers.