Invention Grant
US09171807B2 Semiconductor device in which internal stress in a layer is relaxed to suppress warping
有权
使层内的内部应力松弛以抑制翘曲的半导体装置
- Patent Title: Semiconductor device in which internal stress in a layer is relaxed to suppress warping
- Patent Title (中): 使层内的内部应力松弛以抑制翘曲的半导体装置
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Application No.: US14026003Application Date: 2013-09-13
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Publication No.: US09171807B2Publication Date: 2015-10-27
- Inventor: Yoshiharu Takada
- Applicant: Kabushiki Kaisha Toshiba
- Applicant Address: JP Minato-ku
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Minato-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2012-224218 20121009
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/00 ; H01L23/31
Abstract:
According to one embodiment, a semiconductor device includes a semiconductor layer, an electrode, and an insulating portion. The semiconductor layer has a first surface. The electrode is provided on the first surface of the semiconductor layer. The insulating portion includes a first layer and a second layer. The first layer covers the electrode on the first surface of the semiconductor layer and has a first internal stress along the first surface. The second layer is provided on the first layer and has a second internal stress in a reverse direction of the first internal stress.
Public/Granted literature
- US20140097449A1 SEMICONDUCTOR DEVICE Public/Granted day:2014-04-10
Information query
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