Provided is an electronic device including a semiconductor memory which includes a cell array region having a first variable resistance element and a peripheral circuit region having a decoupling capacitor, the decoupling capacitor including a bottom electrode, a dielectric layer pattern, and a top electrode. The cell array region may include: a first gate; a first contact over the first gate; a second contact over an active region at one side of the first gate; and the first variable resistance element over the second contact, and the peripheral circuit region may include: a second gate formed of the same material at the same level as the first gate; the bottom electrode disposed over the second gate and formed at the same level as the first contact; and the dielectric layer pattern and the top electrode disposed over the bottom electrode.