An isolation circuit includes a first multiplexer, a D flip-flop, a second multiplexer, an OR gate, and an AND gate. The first multiplexer selects a data signal or a scan-in signal as a first element output signal according to a scan enable signal. The D flip-flop generates a second element output signal according to the first element output signal. The second element output signal is fed back to the first multiplexer and is used as the data signal. The second multiplexer selects an isolation signal or the second element output signal as a third element output signal according to a test enable signal. The OR gate generates a fourth element output signal according to the scan enable signal and the third element output signal. The AND gate generates a second power domain signal according to a first power domain signal and the fourth element output signal.