Invention Grant
US09177093B2 Routing interconnect of integrated circuit designs with varying grid densities
有权
具有不同电网密度的集成电路设计的路由互连
- Patent Title: Routing interconnect of integrated circuit designs with varying grid densities
- Patent Title (中): 具有不同电网密度的集成电路设计的路由互连
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Application No.: US13753374Application Date: 2013-01-29
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Publication No.: US09177093B2Publication Date: 2015-11-03
- Inventor: Limin He , So-Zen Yao , Wenyong Deng , Jing Chen , Liang-Jih Chao
- Applicant: Cadence Design Systems, Inc.
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: G06F17/50
- IPC: G06F17/50
Abstract:
Routing methods for an integrated circuit design layout are disclosed. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.
Public/Granted literature
- US20140215426A1 ROUTING INTERCONNECT OF INTEGRATED CIRCUIT DESIGNS WITH VARYING GRID DENSITIES Public/Granted day:2014-07-31
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