Invention Grant
- Patent Title: Memory with bit line capacitive loading
- Patent Title (中): 具有位线电容负载的存储器
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Application No.: US13403543Application Date: 2012-02-23
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Publication No.: US09177671B2Publication Date: 2015-11-03
- Inventor: Michael R. Seningen , Michael E. Runas
- Applicant: Michael R. Seningen , Michael E. Runas
- Applicant Address: US CA Cupertino
- Assignee: Apple Inc.
- Current Assignee: Apple Inc.
- Current Assignee Address: US CA Cupertino
- Agency: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.
- Main IPC: G11C7/10
- IPC: G11C7/10 ; G11C29/50 ; G11C29/52 ; G11C11/41
Abstract:
A memory that may allow for the detection of weak data storage cells may include data storage cells, a column multiplexer, a sense amplifier, and a load circuit. The load circuit may include one or more capacitive loads and may be operable to controllably select one or more of the capacitive loads to couple to the input of the sense amplifier.
Public/Granted literature
- US20130223158A1 MEMORY WITH BIT LINE CAPACITIVE LOADING Public/Granted day:2013-08-29
Information query
