Invention Grant
- Patent Title: Die assembly on thin dielectric sheet
- Patent Title (中): 薄电介质片上的模具组装
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Application No.: US14041722Application Date: 2013-09-30
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Publication No.: US09177831B2Publication Date: 2015-11-03
- Inventor: Chia-Pin Chiu , Qing Ma , Robert L. Sankman , Paul B. Fischer , Patrick Morrow , William J. Lambert , Charles A. Gealer , Tyler Osborn
- Applicant: Chia-Pin Chiu , Qing Ma , Robert L. Sankman , Paul B. Fischer , Patrick Morrow , William J. Lambert , Charles A. Gealer , Tyler Osborn
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L21/48 ; H01L23/538 ; H01L23/00 ; H01L23/15 ; H01L21/56 ; H01L23/31

Abstract:
A die assembly formed on a thin dielectric sheet is described. In one example, a first and a second die have interconnect areas. A dielectric sheet, such as glass, silicon, or oxidized metal is applied over the interconnect areas of dies. Conductive vias are formed in the dielectric sheet to connect with pads of the interconnect areas. A build-up layer includes routing to connect pads of the first die interconnect area to pads of the second die interconnect area through the conductive vias and a cover is applied over the dies, the dielectric sheet, and the build-up layer.
Public/Granted literature
- US20150091182A1 DIE ASSEMBLY ON THIN DIELECTRIC SHEET Public/Granted day:2015-04-02
Information query
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