Invention Grant
US09177848B2 Semiconductor wafer having through-hole vias on saw streets with backside redistribution layer
有权
半导体晶片在具有背面再分配层的锯面街道上具有通孔通孔
- Patent Title: Semiconductor wafer having through-hole vias on saw streets with backside redistribution layer
- Patent Title (中): 半导体晶片在具有背面再分配层的锯面街道上具有通孔通孔
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Application No.: US13543618Application Date: 2012-07-06
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Publication No.: US09177848B2Publication Date: 2015-11-03
- Inventor: Byung Tai Do , Heap Hoe Kuan , Linda Pei Ee Chua
- Applicant: Byung Tai Do , Heap Hoe Kuan , Linda Pei Ee Chua
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC, Ltd.
- Current Assignee: STATS ChipPAC, Ltd.
- Current Assignee Address: SG Singapore
- Agency: Patent Law Group: Atkins and Associates, P.C.
- Agent Robert D. Atkins
- Main IPC: H01L23/04
- IPC: H01L23/04 ; H01L21/683 ; H01L21/768 ; H01L23/48 ; H01L25/03 ; H01L25/065 ; H01L23/00

Abstract:
A semiconductor wafer contains a plurality of die with contact pads disposed on a first surface of each die. Metal vias are formed in trenches in the saw street guides and are surrounded by organic material. Traces connect the contact pads and metal vias. The metal vias can be half-circle vias or full-circle vias. The metal vias are surrounded by organic material. Redistribution layers (RDL) are formed on a second surface of the die opposite the first surface. The RDL and through-hole vias (THV) provide expanded interconnect flexibility to adjacent die. Repassivation layers are formed between the RDL on the second surface of the die for electrical isolation. The die are stackable and can be placed in a semiconductor package with other die. The RDL provide electrical interconnect to the adjacent die. Bond wires and solder bumps also provide electrical connection to the semiconductor die.
Public/Granted literature
- US20120273967A1 Semiconductor Wafer Having Through-Hole Vias on Saw Streets with Backside Redistribution Layer Public/Granted day:2012-11-01
Information query
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