Invention Grant
- Patent Title: Electrically isolated power semiconductor package with optimized layout
- Patent Title (中): 电隔离功率半导体封装，优化布局
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Application No.: US14556940Application Date: 2014-12-01
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Publication No.: US09177888B2Publication Date: 2015-11-03
- Inventor: Thomas Spann , Holger Ostmann , Kang Rim Choi
- Applicant: IXYS Corporation
- Applicant Address: US CA Milpitas
- Assignee: IXYS Corporation
- Current Assignee: IXYS Corporation
- Current Assignee Address: US CA Milpitas
- Agency: Imperium Patent Works
- Agent Amir V. Adibi
- Main IPC: H01L21/56
- IPC: H01L21/56 ; H01L23/40 ; H01L23/31 ; H01L23/373 ; H01L23/433 ; H01L23/495 ; H01L23/00 ; H01L21/52
Abstract:
A packaged power semiconductor device is provided with voltage isolation between a metal backside and terminals of the device. The packaged power semiconductor device is arranged in an encapsulant defining a hole for receiving a structure for physically coupling the device to an object. A direct-bonded copper (“DBC”) substrate is used to provide electrical isolation and improved thermal transfer from the device to a heatsink. At least one power semiconductor die is mounted to a first metal layer of the DBC substrate. The first metal layer spreads heat generated by the semiconductor die. In one embodiment, the packaged power semiconductor device conforms to a TO-247 outline and is capable of receiving a screw for physically coupling the device to a heatsink.
Public/Granted literature
- US20150087113A1 ELECTRICALLY ISOLATED POWER SEMICONDUCTOR PACKAGE WITH OPTIMIZED LAYOUT Public/Granted day:2015-03-26
Information query
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