Cathodes of a first group of plural transfer thyristors are connected with a first transfer signal line, and also connected with a first reception terminal through a first current limiting resistance. A first transfer signal is transmitted to the first reception terminal. Cathodes of a second group of the plural transfer thyristors are connected with a second transfer signal line, and also connected with a second reception terminal through a second current limiting resistance. A second transfer signal is transmitted to the second reception terminal. The plural transfer thyristors each have an anode, a cathode, a first gate, and a second gate. A three-terminal switch element and a resistance are connected between a second gate of a former transfer thyristor and a first gate of a later transfer thyristor, the former and later transfer thyristors being closely arranged upstream and downstream transfer thyristors among the plural transfer thyristors.