Invention Grant
- Patent Title: Printed circuit board assembly and solder validation method
- Patent Title (中): 印刷电路板组装和焊接验证方法
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Application No.: US13766237Application Date: 2013-02-13
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Publication No.: US09179536B2Publication Date: 2015-11-03
- Inventor: Steven F. Gawron , Jonathan Dahlstrom
- Applicant: Lear Corporation
- Applicant Address: US MI Southfield
- Assignee: Lear Corporation
- Current Assignee: Lear Corporation
- Current Assignee Address: US MI Southfield
- Agency: Brooks Kushman P.C.
- Main IPC: H05K3/00
- IPC: H05K3/00 ; H05K1/02 ; H05K1/18 ; H05K3/06

Abstract:
A solder validation method for a printed circuit board (PCB) having a pin hole extending through the PCB, an electrically conductive trace on a surface of the PCB, and an electrically conductive pin inserted through the pin hole includes the following. An electrically non-conductive portion is provided on the surface of the PCB between the pin hole and the trace such that the non-conductive portion electrically isolates the pin from the trace. After a soldering process intended to solder the pin and the trace together, a soldered connection between the pin and the trace is detected as being absent when no electrical continuity is between the pin and the trace as a soldered connection between the pin and the trace has to be present to provide the electrical continuity due to the pin and the trace otherwise being electrically isolated from one another by the non-conductive portion.
Public/Granted literature
- US20130322041A1 PRINTED CIRCUIT BOARD ASSEMBLY AND SOLDER VALIDATION METHOD Public/Granted day:2013-12-05
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