Some embodiments relate to a system that pre-colors word lines and control lines within a memory cell to avoid timing delays that result from processing variations introduced through multiple patterning lithography processes. The system has a memory element that stores a graphical IC layout with a memory circuit having layout features including a plurality of word lines and a plurality of Y-control lines. A pre-coloring element pre-colors one or more of the plurality of word lines and Y-control lines, to indicate that pre-colored word lines and Y-control lines are to be formed on a same mask of a multiple mask set used for a multiple patterning lithography process. A decomposition element assigns different colors to uncolored layout features of the memory circuit, to indicate that different colored memory features are to be formed on different masks of the multiple mask set.