Invention Grant
- Patent Title: Delay circuit and semiconductor memory device
- Patent Title (中): 延迟电路和半导体存储器件
-
Application No.: US14201592Application Date: 2014-03-07
-
Publication No.: US09183905B2Publication Date: 2015-11-10
- Inventor: Osamu Hirabayashi
- Applicant: Kabushiki Kaisha Toshiba
- Applicant Address: JP Minato-Ku, Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Minato-Ku, Tokyo
- Agency: White & Case LLP
- Priority: JP2013-132938 20130625
- Main IPC: G11C7/22
- IPC: G11C7/22 ; G11C11/419 ; G11C7/08 ; G11C7/04
Abstract:
According to an embodiment, a load adjusting circuit adjusts the load of an inverter circuit based on a threshold voltage of a first conductive type transistor provided on the inverter circuit, and a driving force adjusting circuit adjusts the driving force of the inverter circuit based on the threshold voltage of the first conductive type transistor.
Public/Granted literature
- US20140376319A1 DELAY CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE Public/Granted day:2014-12-25
Information query
