Invention Grant
- Patent Title: Latch-up suppression and substrate noise coupling reduction through a substrate back-tie for 3D integrated circuits
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Application No.: US14072707Application Date: 2013-11-05
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Publication No.: US09184110B2Publication Date: 2015-11-10
- Inventor: Jamil Kawa , Victor Moroz
- Applicant: SYNOPSYS, INC.
- Applicant Address: US CA Mountain View
- Assignee: SYNOPSYS, INC.
- Current Assignee: SYNOPSYS, INC.
- Current Assignee Address: US CA Mountain View
- Agency: Haynes Beffel & Wolfeld LLP
- Main IPC: H01L29/40
- IPC: H01L29/40 ; H01L23/48 ; H01L21/768 ; H01L23/00
Abstract:
Roughly described, an integrated circuit device has a conductor extending entirely through the substrate, connected on one end to the substrate topside surface and on the other end to the substrate backside surface. In various embodiments the conductor is insulated from all RDL conductors on the backside of the substrate, and/or is insulated from all conductors and device features on any below-adjacent chip in a 3D integrated circuit structure. Methods of fabrication are also described.
Public/Granted literature
Information query
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