Invention Grant
US09187310B2 Wafer-level packaging of a MEMS integrated device and related manufacturing process
有权
MEMS集成器件的晶圆级封装及相关制造工艺
- Patent Title: Wafer-level packaging of a MEMS integrated device and related manufacturing process
- Patent Title (中): MEMS集成器件的晶圆级封装及相关制造工艺
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Application No.: US14030867Application Date: 2013-09-18
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Publication No.: US09187310B2Publication Date: 2015-11-17
- Inventor: Federico Giovanni Ziglioli
- Applicant: STMicroelectronics S.r.l.
- Applicant Address: IT Agrate Brianza
- Assignee: STMicroelectronics S.r.l.
- Current Assignee: STMicroelectronics S.r.l.
- Current Assignee Address: IT Agrate Brianza
- Agency: Seed IP Law Group PLLC
- Priority: ITTO2012A0827 20120924
- Main IPC: B81B3/00
- IPC: B81B3/00 ; B81B7/00 ; B81C1/00

Abstract:
A wafer-level package for a MEMS integrated device, envisages: a first body integrating a micromechanical structure; a second body having an active region integrating an electronic circuit, coupled to the micromechanical structure; and a third body defining a covering structure for the first body. The second body defines a base portion of the package and has an inner surface coupled to which is the first body, and an outer surface provided on which are electrical contacts towards the electronic circuit; a routing layer has an inner surface set in contact with the outer surface of the second body and an outer surface that carries electrical contact elements towards the external environment. The third body defines a covering portion for covering the package and is directly coupled to the second body for closing a housing space for the first body.
Public/Granted literature
- US20140084397A1 WAFER-LEVEL PACKAGING OF A MEMS INTEGRATED DEVICE AND RELATED MANUFACTURING PROCESS Public/Granted day:2014-03-27
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