Invention Grant
- Patent Title: Integrated bondline spacers for wafer level packaged circuit devices
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Application No.: US14202756Application Date: 2014-03-10
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Publication No.: US09187312B2Publication Date: 2015-11-17
- Inventor: Roland Gooch , Buu Diep , Thomas Allan Kocian , Stephen H. Black , Adam M. Kennedy
- Applicant: Raytheon Company
- Applicant Address: US MA Waltham
- Assignee: RAYTHEON COMPANY
- Current Assignee: RAYTHEON COMPANY
- Current Assignee Address: US MA Waltham
- Agency: Cantor Colburn LLP
- Main IPC: H01L21/30
- IPC: H01L21/30 ; B81B7/00 ; B81C1/00 ; H01L23/053 ; H01L23/00

Abstract:
A method of forming a wafer level packaged circuit device includes forming a device wafer, the device wafer including a first group of one or more material layers left remaining in a first region of a substrate of the device wafer; and forming a cap wafer configured to be attached to the device wafer, the cap wafer including a second group of one or more material layers left remaining in a second region of a substrate of the cap wafer; wherein a combined thickness of the first and second groups of one or more material layers defines an integrated bond gap control structure upon bonding of the device wafer and the cap wafer.
Public/Granted literature
- US20140193948A1 INTEGRATED BONDLINE SPACERS FOR WAFER LEVEL PACKAGED CIRCUIT DEVICES Public/Granted day:2014-07-10
Information query
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