Invention Grant
US09190150B2 Non-volatile memory device having 3D memory cell array with improved wordline and contact layout
有权
具有改进的字线和接触布局的具有3D存储单元阵列的非易失性存储器件
- Patent Title: Non-volatile memory device having 3D memory cell array with improved wordline and contact layout
- Patent Title (中): 具有改进的字线和接触布局的具有3D存储单元阵列的非易失性存储器件
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Application No.: US14017435Application Date: 2013-09-04
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Publication No.: US09190150B2Publication Date: 2015-11-17
- Inventor: Keishi Sakanushi
- Applicant: Kabushiki Kaisha Toshiba
- Applicant Address: JP Minato-ku
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Minato-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2013-064629 20130326
- Main IPC: H01L29/78
- IPC: H01L29/78 ; G11C16/04 ; H01L27/115 ; H01L29/792
Abstract:
According to one embodiment, a semiconductor memory device includes a semiconductor substrate, a memory cell array including a plurality of stacked memory cells, a plurality of first wirings electrically connected to the plurality of memory cells, a plurality of first contacts electrically connected to part of the plurality of first wirings and arranged in a first direction parallel to the semiconductor substrate, a plurality of second contacts electrically connected to part of the plurality of first wirings and arranged in the first direction alternately with the first contacts, a plurality of third contacts electrically connected to the first contacts and displaced from the first contacts in the first direction, and a plurality of fourth contacts electrically connected to the second contacts and displaced from the second contacts in a second direction perpendicular to the first direction.
Public/Granted literature
- US20140293700A1 SEMICONDUCTOR MEMORY DEVICE Public/Granted day:2014-10-02
Information query
IPC分类:
