Invention Grant
- Patent Title: NAND flash memory employing bit line charge/discharge circuit
- Patent Title (中): NAND闪存采用位线充电/放电电路
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Application No.: US13847201Application Date: 2013-03-19
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Publication No.: US09190156B2Publication Date: 2015-11-17
- Inventor: Mario Sako
- Applicant: Kabushiki Kaisha Toshiba
- Applicant Address: JP Tokyo
- Assignee: KABUSHIKI KAISHA TOSHIBA
- Current Assignee: KABUSHIKI KAISHA TOSHIBA
- Current Assignee Address: JP Tokyo
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2012-103947 20120427
- Main IPC: G11C16/24
- IPC: G11C16/24 ; G11C16/26 ; H01L27/115 ; G11C16/04 ; G11C29/02 ; G11C29/12

Abstract:
According to one embodiment, a nonvolatile semiconductor storage device includes a memory cell array where memory cells are arranged in a row direction and a column direction in a matrix shape; word lines which select the memory cell in the row direction; bit lines which select the memory cells in the column direction; a sense amplifier circuit which determines values stored in the memory cells based on states of the bit line; and a charge/discharge circuit which is formed in a well where the memory cell array is arranged and which charges or discharges the bit lines.
Public/Granted literature
- US20130286748A1 NONVOLATILE SEMICONDUCTOR STORAGE DEVICE Public/Granted day:2013-10-31
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