Invention Grant
US09190157B2 Semiconductor device including memory cell having charge accumulation layer
有权
包括具有电荷累积层的存储单元的半导体器件
- Patent Title: Semiconductor device including memory cell having charge accumulation layer
- Patent Title (中): 包括具有电荷累积层的存储单元的半导体器件
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Application No.: US14341662Application Date: 2014-07-25
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Publication No.: US09190157B2Publication Date: 2015-11-17
- Inventor: Mitsuhiro Noguchi , Kenji Gomikawa
- Applicant: KABUSHIKI KAISHA TOSHIBA
- Applicant Address: JP Minato-ku
- Assignee: KABUSHIKI KAISHA TOSHIBA
- Current Assignee: KABUSHIKI KAISHA TOSHIBA
- Current Assignee Address: JP Minato-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2007-317582 20071207
- Main IPC: H01L27/115
- IPC: H01L27/115 ; G11C16/24 ; H01L27/02 ; H01L27/105 ; G11C16/30

Abstract:
A semiconductor device includes MOS transistors, capacitor elements, a voltage generating circuit, a contact plug, and a memory cell. The MOS transistor and the capacitor element are formed on a first one of the element regions and a second one of the element regions, respectively. In the voltage generating circuit, current paths of the MOS transistors are series-connected and the capacitor elements are connected to the source or drain of the MOS transistors. The contact plug is formed on the source or the drain to connect the MOS transistors or one of the MOS transistors and one of the capacitor elements. A distance between the gate and the contact plug both for a first one of the MOS transistors located in the final stage in the series connection is larger than that for a second one of the MOS transistors located in the initial stage in the series connection.
Public/Granted literature
- US20140334234A1 SEMICONDUCTOR DEVICE INCLUDING MEMORY CELL HAVING CHARGE ACCUMULATION LAYER Public/Granted day:2014-11-13
Information query
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